Objective 1: Development of high performance InP photonic components on InP membranes enabling 112 Gbaud per lane transmission for intra- and inter- datacentre applications and ultra-fast large-scale integrated optical switches.
Objective 2: Development of high speed InP-HBT electronics components and ICs for interfacing with next generation 112G SERDES.
Objective 3: Development of system-on-chip photonic platform based on the co-integration of actives and passives enabling complex functionalities.
Objective 4: Towards wafer-scale co-integration of InP photonics and InP-HBT electronics for the development of optoelectronic engines with enhanced capabilities.
Objective 5: Intimate integration of optoelectronic engine with ASIC for the development of system-inpackage (SiP) transceiver demonstrators for 1.6T intra- and inter- datacentre applications.
Objective 6: Development of a programmable compact ultra-fast 4×4 and 16×16 optical space switches for low latency intra-datacentre connectivity.
Objective 7: Performance evaluation of the developed TWILIGHT demonstrators under real network conditions and exploitation of project foreground.